1) Field of the Invention
The invention relates to methods and apparatuses for the realization of spectral containment of radio transmissions so that they do not cause adjacent channel interference and, in particular, for the realization of spectral containment of high bitrate digital transmissions such as TDMA or CDMA cellular telephone signals.
2) Discussion of Related Art
Technological advancements have permitted continuous improvements in reducing the size and cost while increasing the battery life of cellular portable telephones. This has made cellular telephones ever more popular. As a result, cellular telephone systems need to expand so as to provide service to ever greater numbers of subscribers.
Pressure on frequency channel availability has led to the development of digital cellular technologies such as the European GSM TDMA system, the U.S. IS-54 digital TDMA cellular standard, and the U.S. IS-95 CDMA standard. All the above systems are characterized by first converting speech to a compressed digital form which is then coded by more or less redundant coding and subsequently transmitted using one or more timeslots in a repeating frame period.
For example, the GSM TDMA system codes speech using convolutional coding and transmits the coded speech using one or two out of 16 timeslots depending on whether a half-rate or a full-rate channel is allocated. An IS-54 system also convolutionally codes speech and then transmits it using one or two out of six timeslots. An IS-95 system uses convolutional coding plus bit repetition and transmits the speech using 2, 4, 8 or 16 out of 16 timeslots depending on whether the speech sound is a voiced sound, non-voiced sound or silence/background noise. In all cases therefore, the bitrate of speech is first compressed to remove natural redundance and then the bitrate is increased by using intelligent coding to obtain a higher bitrate stream for transmission that is more tolerant of interference.
A transmitter for such digitally coded signals preferably comprises a balanced quadrature modulator. FIG. 1 illustrates a prior art arrangement of a quadrature modulator for synthesizing an arbitrarily modulated signal. A digital signal processor (DSP) 30 calculates time-spaced samples of the real and imaginary parts of a desired complex modulation. The real part is given by the desired amplitude times the cosine of the desired phase angle, while the imaginary part is given by the amplitude times the sine of the phase angle. In this way both Amplitude Modulated (AM) signals or Phase Modulated (PM) signals can be generated, or signals comprising both, the result of which is generally known as complex modulated signals. The numerical samples calculated by the DSP 30 are transferred to a pair of Digital-to-Analog (D-to-A) convertors 31 that convert each numerical sample pair into a pair of analog voltages known as I (In-phase) and Q (Quadrature) signals. A sequence of such numerical samples generates I and Q waveforms but in a stepwise fashion.
The steps in the waveforms cause undesirable spectral components that would interfere with adjacent radio channels unless suppressed. Some techniques for D-to-A conversion provide interpolation between samples giving sloping waveforms between adjacent sample values, which reduces but does not sufficiently eliminate the undesired components. Consequently, I and Q smoothing filters 32 are necessary. These are low-pass filters that pass all modulation spectral components of interest but suppress the higher frequency components of the spectrum associated with the stepwise or piecewise linear I,Q waveforms from the D-to-A convertors 31.
The smoothed I,Q waveforms are applied to a pair of balanced modulators 33 together with cosine and sine carrier frequency signals, this arrangement being known as a quadrature modulator. The arrangement described so far and illustrated in FIG. 1 belongs to the well-known prior art.
In summary, the DSP 30 produces numerical I and Q waveforms representative of the desired digital or analog modulation and then D-to-A convertors 31 convert the numerical I,Q representations to analog I,Q modulating waveforms. Filters 32 remove discontinuities due to the finite time sampling and quantization of the numerical I,Q signals to produce continuous I,Q waveforms, thus avoiding spectral splatter into adjacent radio channels. The smoothed I,Q waveforms are applied to sine and cosine radio frequency-carriers using quadrature modulator 33.
It is important for accurate signal generation that (1) the two balanced modulators are accurately matched, (2) the levels of the I and Q signals are accurately controlled relative to each other, and (3) the balanced modulators have low carrier leakage or offset, that is, the output signal of a balanced modulator should be zero when its respective I or Q modulating signal is zero.
Since the I and Q signals vary from positive to negative, if a circuit is required to operate only from a single positive supply, then the zero point of an I or Q waveform cannot be defined to be zero voltage, but must be defined to be some positive reference voltage such as half the supply voltage. Then when an I or Q waveform swings below this reference voltage it will be interpreted as negative, and positive when it swings above.
Unfortunately, it is difficult to generate a reference voltage from the DSP 30 that is exactly equal to the voltage the D-to-A convertors supply with an input numerical value of zero. This problem is overcome by use of the balanced configuration shown in FIG. 2 and disclosed in U.S. Pat. No. 5,530,722, herein incorporated by reference, which uses special D-to-A conversion techniques to generate I and Q signals as well as their complements I and Q.
In FIG. 2, instead of using the D-to-A convertors 31 of FIG. 1, the numerical I and Q signals from DSP 30 are transferred to a delta-sigma (.DELTA.-.SIGMA.) convertor 41. This device is built according to known art to generate a high bitrate stream of binary `1`s and `0`s having a short-term average value proportional to the numerical input value. With a maximum possible numerical input value the bit stream produced would be 1111 . . . (the voltage of a `1` condition being equal to the chosen supply voltage) while the minimum numerical input value will generate the bit pattern 00000 . . . A half-scale numerical input will produce the bit stream 1010101010 . . . having an average voltage equal to half the supply voltage. According to an aspect of the invention disclosed in U.S. Pat. No. 5,539,722, extra invertor gates 42 are provided at the output of each delta-sigma convertor 41 to additionally generate the complementary bitstreams. That means when delta-sigma convertors 41 produce a bit stream 100100100100 . . . having a mean of 1/3 the supply voltage, the complementary bit stream will be 011011011011 . . . having a mean of 2/3rds the supply voltage. The difference between these two is 1/3-2/3=-1/3 of the supply voltage. If the convertor produces 111011101110 . . . having a mean of +3/4 of the supply voltage then the complementary signal 000100010001 . . . will have the mean of 1/4 of the supply voltage, so that the difference is 3/4-1/4=+1/2 of the supply voltage. Consequently, by using the difference between the convertor output signal and its complement to represent an I or Q signal, the value represented can be positive or negative even with a single positive voltage supply, and no reference voltage need be generated. The balanced mixers 43 are therefor provided with balanced, two-wire inputs rather than single-ended inputs, that are responsive to the difference in the signals on the two wires and unresponsive to the absolute or common-mode voltage (sum of the voltages) on the two wires.
High bitrate delta-sigma modulation bitstreams are simply converted to the analog voltage they represent by forming the moving average voltage over a large number of bits. This may be done using a continuous-time, low-pass filter having a bandwidth which is a small fraction of the bitrate, but still sufficient to pass all desired modulation components. For the balanced signal configuration developed in this invention, balanced filters 44 are interposed between the delta-sigma convertor outputs and the I,Q balanced modulators 43.
In summary, delta-sigma convertors 41 convert the numerical sample values from DSP 30 to high bitrate streams wherein instantaneous waveform values are represented by the proportion of ones to zeros in the bitstream, i.e., by the average mark/space ratio. The inverters 42 form complementary bitstreams such that the difference in mark space ratio forms a balanced signal that can more easily represent both positive and negative instantaneous waveform values. The high bitrate fluctuations are removed by balanced filters 44 to obtain continuous, smoothed I,Q waveforms which are applied to balanced inputs of quadrature modulator 43, as disclosed in U.S. Pat. No. 5,530,722, which is a continuation-in-part of U.S. patent application Ser. No. 07/967,027, now U.S. Pat. No. 5,745,523 which is also incorporated herein by reference. The parent applications disclose the advantages of using balanced I,Q signals representing a complex modulating signal waveform by means of high bitrate sigma-delta modulation streams and their complements.